pipeline architecture meaning in English
管线结构
Examples
- This paper introduces the history of the gpu firstly , and then it analyses the pipeline architecture of gpu . finally , it introduces several types of program languages of gpu
本文首先介绍了可编程图形硬件的发展，然后分析了它的流水线结构，最后介绍了几种最新的编程语言。 - And it presents the method that the filter is analyze to lifting process . we use the folding and pipeline architecture to deal with this kind of novel dwt
本论文提出一种根据jpeg2000标准将9 7滤波器分解为提升过程矩阵乘积的形式，使用流水线的思想的新型离散小波变换结构。 - After analyzing and comparing different partition rules , md32 pipeline architecture is finally defined , which meets the required instruction function , frequency and timing spec of md32 . a complete set of creative design method for risc / dsp md32 micro - architecture is presented , such as parallel design , internal pipeline , central control , etc . thanks to the adoption of these design methodology , control path and data path are separated , circuit delay is reduced , and complex instruction operations are balanced among multiple pipeline stages
它们将若干复杂指令操作均匀分配在几个流水节拍内完成，实现了任意窗口寻址等复杂指令操作，将整个处理器的数据通路与控制通路分离，减小了电路时延，从而满足了risc dsp不同指令功能和系统时钟频率的要求，构成了统一的、紧密联系的、协调的md32系统结构。 - The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu , and dwells on 64 - bit vega cpu characteristic , and details the eda technology and the main flow of asic design , and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation , and details cache architecture and mmu . the master dissertation dwells on virtual address translating into physical address , instruction cache finding address and instruction fetching , too
详细的阐述了64位vegacpu的特点，阐述了eda技术和asic设计的主要流程，阐述了vegacpu流水线结构、流水线操作、流水线暂停和异常处理，虚拟指令地址的结构和产生， mmu结构，包括指令tlb结构和虚拟指令地址向物理指令地址的生成流程， cache结构，寻址原理和指令的写策略，指令高速缓存的寻址原理和结构，以及指令的获取流程。